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U5021M
Digital Window Watchdog Timer
Description
The digital window watchdog timer, U5021M, is a CMOS integrated circuit. In applications where safety is critical, it is especially important to monitor the microcontroller. Normal microcontroller operation is indicated by a cyclically transmitted trigger signal which is received by a window watchdog timer within a defined time window. A missing or a wrong trigger signal makes the watchdog timer reset the microcontroller. The IC is tailored for microcontrollers which can work in both full-power and sleep mode. With additional voltage monitoring (power-on reset and supply voltage drop reset), the U5021M offers a complete monitoring solution for microsystems in automotive and industrial applications.
Features
D Low current consumption: IDD < 100 mA D RC-oscillator D Internal reset during power up and supply voltage drops (POR) D "Short" trigger window for active mode "long" trigger window for sleep mode D Cyclical wake-up of microcontroller in sleep mode D Trigger input D Single wake-up input D Reset output D Enable output
Ordering Information
Extended Type Number U5021M-NFP Package SO8
C VDD R1 VDD C1 Reset 5 6 OSC 8 RC Oscillator OSC 10 nF
95 10605
Remarks
Block Diagram
mC Trigger 2
State machine OSC Input signal conditioning POR Power-on reset POR Test logic 4 Enable External switching circuitry
Mode 3
Wake-up
1
7 GND
Figure 1. Block diagram with external circuit
Rev. A3, 22-May-00
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U5021M
Pin Description
Pin 1 Symbol Function Wake-up Wake-up input (pull-down resistor) There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at the input initiates a reset pulse at Pin 5. Trig Trigger input (pull-up resistor) It is connected to the microprocessor's trigger signal. Mode Mode input (pull-up resistor) The processor's mode signal initiates the switchover between the long and the short watchdog time. Ena Enable output (push-pull) It is used for the control of peripheral components. It is activated after the processor triggers three times correctly. Reset Reset output (open drain) Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog period. VDD Supply voltage GND Ground, reference voltage Osc RC oscillator
Wake-up 1 Trig 2 Mode 3 Ena 4
8
Osc 2
7 GND 3 6 VDD 5 Reset
4
Figure 2. Pinning
5
6 7 8
Functional Description
Supply Voltage, Pin 6
The U5021M requires a stabilized supply voltage VDD = 5 V " 5% to comply with its electrical characteristic. An external buffer capacitor of C = 10 nF may be connected between Pin 6 and GND. where t + 1.35 ) 1.57 R1 (C 1 ) 0.01) R 1 in kW, C1 in nF and t in ms
RC-Oscillator, Pin 8
The clock frequency, f, can be adjusted with the components R1 and C1 according to the formula: f+1 t
The clock frequency determines all time periods of the logic part as shown in the last section of the data sheet (timing). With an appropriate selection of components, the clock frequency, f, is nearly independent of the supply voltage, as shown in figure 3. Frequency tolerance Dfmax = 10% with R1 " 1%, C1 = " 5%.
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Rev. A3, 22-May-00
U5021M
1000.00
100.00
t (ms)
10.00
4.5 V 5.0 V 5.5 V C1 = 500 pF
1.00 1 10 100 1000
95 10642
R1 (kW)
Figure 3. Period t vs. R1, @ C1 = 500 pF
Pin 6 V DD Reset Out
to t1
t6
Pin 5
Mode
Figure 4. Power-on reset and switch-over mode
Pin 3
95 10643
Supply Voltage Monitoring, Pin 5
During ramp-up of the supply voltage and in the case of supply-voltage drops the integrated power-on reset (POR) circuitry sets the internal logic to a defined basic status and generates a reset pulse at the reset output, Pin 5. A hysteresis in the POR threshold prevents the circuit from oscillating. During ramp-up of the supply voltage the reset output stays active for t0 in order to bring the microcontroller into its defined reset status (see figure 4). Pin 5 has an open-drain output.
(see figure 4), the watchdog generates a reset pulse, t6, and t1 starts again. Microcontroller and watchdog are synchronized with the switch-over mode time, t1, each time a reset pulse is generated.
Microcontroller in Active Mode
Monitoring with the "Short" Trigger Window
After the switch-over mode, the watchdog works in the short watchdog mode and expects a trigger pulse from the microcontroller within the defined time window, t3 (enable time). The watchdog generates a reset pulse which resets the microcontroller if D the trigger pulse duration is too long, D the trigger pulse is within the disable time, t2 D there is no trigger pulse
Switch-over Mode Time, Pin 3
The switch-over mode time enables the synchronous operation of microcontroller and watchdog. After the power-on reset time, the watchdog has to be switched to its monitoring mode by the microcontroller with a "low" signal transmitted to the mode pin (Pin 3) within the timeout period, t1. If the low signal does not occur within t1
Rev. A3, 22-May-00
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U5021M
V DD Reset Out Pin 6
to
t1
Pin 5
t2
Mode
t3
Pin 3
Pin 2 Trigger
95 10644
Figure 5. Pulse diagram with no trigger pulse during the short watchdog time
Figure 5 shows the pulse diagram with a missing trigger pulse. Figure 6 shows a correct trigger sequence. The positive edge of the trigger signal starts a new monitoring cycle with the disable time, t2. To ensure correct operation of the microcontroller, the watchdog needs to be triggered three times correctly before it sets its enable output. This feature is used to activate or deactivate safety-critical components which have to be switched to a certain condition (emergency status) in the case of a microcontroller malfunction. As soon as there is an incorrect trigger sequence, the enable signal is reset and it takes a sequence of three correct triggers again before enable is active.
Microcontroller in Sleep Mode
Monitoring with the "Long" Trigger Window
The long watchdog mode allows cyclical wake-up of the microcontroller during sleep mode. As in short watchdog mode, there is a disable time, t4, and an enable time, t5, in which a trigger signal is accepted. The watchdog can be switched from the short trigger window to the long trigger window with a "high" potential at the mode pin (Pin 3). In contrast to the short watchdog mode, the time periods are now much longer and the enable output remains inactive so that other components can be switched off to effect a further decrease in current consumption. As soon as a wake-up signal at the wake-up input (Pins 1) is detected, the long watchdog mode ends, a reset pulse wakes-up the sleeping microcontroller and the normal monitoring cycle starts with the mode switch-over time.
.
VDD
Pin 6
t0
Reset Out
t1
Pin 5
t3 t2 t2
Pin 3 Pin 2
Mode
Trigger
t trig
Enable Pin 4
95 10645
Figure 6. Pulse diagram of a correct trigger sequence during the short watchdog time
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Rev. A3, 22-May-00
U5021M
Figure 7 shows the switch-over from the short to the long watchdog mode. The wake-up signal during the enable time, t5, activates a reset pulse, t6. Reset out The watchdog can be switched back from the long to the short watchdog mode with a low potential at the mode pin (Pin 3).
t6
t1
Pin 5
Wake-up
Pins 1
t4
Mode
t5
Pin 3
t2
Trigger Pin 2
Enable
95 10646
Pin 4
Figure 7. Pulse diagram of the long watchdog time
Rev. A3, 22-May-00
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U5021M
State Diagram
The kernal of the watchdog is a finite state machine. Figure 8 shows the state diagram. All possible states and transmissions are shown. Many transmissions are controlled by an internal timer. The numbers for the time-outs are the same as on the pulse diagrams.
Reset state
time out t 0 mode = 1
Mode switch state
mode = 0
Short window disable state
mode = 0
Long window disable state
time out t 1
time out t 2 trg_ok = 1 mode = 1 mode = 0
time out t4 trg_ok = 1
time out t 6
trg = 0 time out t 3
Short window enable state
trg_err = 1
Long window enable state
trg_err = 1
Reset out state
time out t 5 OR wedge = 1 Note: "mode" and "trg" are the debounced input signals from the pins MODE and TRG trg_ok = 1 after the rising edge of the trg signal trg_err = 1 when the trg signal low period is too long
trg = 0 OR wedge = 1
wedge = 1 after detecting the debounced changing of an signal level from the WUP pin every state change restarts the internal timer Figure 8. State diagram
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Rev. A3, 22-May-00
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Thermal Resistance
Junction ambient Input voltage Ambient temperature range Storage temperature range Parameter Symbol RthJA VIN Tamb Tstg -0.4 V to VDD + 0.4 V -40 to +125 -55 to +150 Value 180 Unit K/W V C C VDD = 5V, Tamb = -40 to 125_C, reference point is Pin 7, unless otherwise specified
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Absolute Maximum Ratings
Supply voltage Output current Parameter Symbol VDD IOUT Value 6.5
Rev. A3, 22-May-00
Electrical Characteristics
Leakage current
Power-on reset hysteresis Inputs Logical 'high' Logical 'low' Hysteresis Input voltage range Input current Input current Outputs Max. output current Logical output 'low' Logical output 'high'
Parameter Supply voltage Current consumption Power-on reset
VOUT = 5 V,
Pins 4 and 5 IOUT = -1 mA, Pins 4 and 5 IOUT = -1 mA, Pin 4
Test Conditions / Pins Symbol Pin 6 VDD R1 = 66 kW Pin 6 IDD Release reset state with rising VPOR1 voltage at Pin 6 Get reset state with falling VPOR2 voltage at Pin 6 VPOR_hys Pins 1, 2, and 3 VIH VIL VIN_hys VIN Pins 2 and 3 I IN1 Pin 1 I IN2
Pin 5
IOUT VOL VOH
Ileak
VDD - 0.2
Min. 4.5
0.6 -0.3 5 -20
3.4
3.8
3.9
-2
40
"2
Typ.
U5021M
1.6 1.4 VDD+0.3 20 -5
Max. 5.5 60 4.5
200
2 0.2
4.4
2
Unit V mA
Unit V A V
mA V V
mV
A
V V V V A A
V
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*)
Package Information
VDD = 5V, Tamb = -40 to 125_C, reference point is Pin 7, unless otherwise specified Parameter Test Conditions / Pins Symbol Min. Typ. Timing Frequency deviation *) R1 = 66 k, C1 = 470 pF , f VDD = 4.5 to 5.5 V Debounce time Pins 2 and 3 3 Debounce time Pin1 96 Max. trigger pulse length ttrgmax 45 Power-up reset time to 201 Switch over mode time t1 1112 Disable time Short watchdog window t2 130 Enable time Short watchdog window t3 124 Disable time Long watchdog window t4 71970 Enable time Long watchdog window t5 30002 Reset-out time t6 40
Electrical Characteristics (continued)
Dimensions in mm
Package SO8
U5021M
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Frequency deviation depends also on the tolerances of the external components 0.4 1 8 1.27 5.00 4.85 3.81 4 5 1.4 0.25 0.10
technical drawings according to DIN specifications
6.15 5.85
3.8
3.7
5.2 4.8
13034
0.2
Rev. A3, 22-May-00 Max. 4 128 5 Unit cyc cyc cyc cyc cyc cyc cyc cyc cyc cyc %
U5021M
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
2.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A3, 22-May-00
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